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Cheatography

Byte ordering of 0x01234567

Byte repres­ent­ation of ints

Bit operations (integral data type)

Logical operators

Unsigned integers

2's complement

2's complement

Converting 2's C to decimal

Floating Point Rep

Encoding

Precision

Normalized encoding

Normalized encoding example

Denorm­alized encoding

Specia­lized encoding

 

movq operand combo

Address comput­ation

Multip­lic­ation

Division

SetX dest: only set lower 1 byte of register

Jumping

2 operand instru­ctions

one operand instru­ctions

useful instru­ction for division

Setting condition codes

Implicitly setting condition code: addq src, dest

Bad cases for condit­ional move

Effect of operations

Logical Operations
CF=0, OF=0
shift
CF=value of last bit shifted out; OF=0
INC, DEC
OF and ZF may change, CF unchanged

Explicitly setting condition codes

cmpl b, a
a-b result not stored anywhere
testq b, a
a&b result not stored anywhere

When are local variables in stack?

Enough registers
No reference to & so no need to go to memory
No arrays, structures

When P(caller) calls Q

Structure repres­ent­ation

Procedure data flow

Register usage

Register usage contd

Popq dest (for stack)

Array access

 

Cache structure

Cache calcul­ation

Cache miss

3 cases
compul­sory, capacity, conflict
How to reduce miss
block size++, associ­ati­vity++, cache size++
Reducing miss penalty
write through (update all) vs write back (update when needed)
 
multilevel cache (optimize hit rate L1, miss rate L2)
Replac­ement policies
LRU, LFU, FIFO, rand

Cache access time

Why Linkers

Source code to execution

Resolving symbols

Why VM

memory management and protection
permission bits; uses main effici­ent­ly(send unneeded to disk)
Process isolat­ion­/memory protection
own add spaces; can't interfere with another's memory
loading linking simplified

VP partit­ioned to 3 subsets

Unallo­cated
not yet created, no data, no space
Uncach­ed/­cached
currently cached/not cached

Address transl­ation w page table

Page hit

page fault

Speed: TLB hit, mem access-1

TLB miss (rare with high assoc): 3 mem accesses

size-- multilevel page table

cache and VM

cache uses PA, since with VA, although can be accessed asap, aliasing, 2 VA may map to same block, would not know which one

mem alloc challenges

memory utiliz­ation (sum of malloc'd data/heap size)
good perfor­mance (mallo­c/free calls return quick)
constr­aints: can't modify malloc'd memory; can't move malloc'd block

implicit free list with footer and header

explicit free list (pointer don't space+)

Seg list

classes of exceptions

exception examples

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