Combinational logic
Definition
-
Combinational Circuit: Output depends only on current inputs; no memory.
-
Sequential Circuit: Output depends on current inputs and past states (memory)
Key Differences
| Feature | Combinational Circuit | Sequential Circuit |
|----------------------|--------------------------------|-------------------------------|
|
Output Dependency | Current inputs only | Current inputs + past states |
|
Memory | No memory | Has memory (e.g., flip-flops) |
|
Feedback | No feedback loop | Includes feedback loop |
|
Clock Signal | Not required | Requires a clock signal |
|
Time Dependency | Outputs appear immediately | Outputs depend on clock cycles |
Examples
-
Combinational Circuit:
- Half Adder: Adds two inputs, outputs Sum = \( A XOR B ), Carry = \( A AND B ).
-
Sequential Circuit:
- D Flip-Flop: Stores 1 bit of data; updates on clock edge.
Applications
-
Combinational Circuits:
- Adders, multiplexers, encoders, decoders.
-
Sequential Circuits:
- Counters, shift registers, memory units.
Summary
-
Combinational Circuits:
- Simple, stateless, used for logical operations.
-
Sequential Circuits:
- Complex, state-based, used for time-sensitive or memory-based tasks.
For AND(also minterm) gates
-
Identity: AND-ing anything with
1
keeps it the same.
-
Null: AND-ing anything with
0
makes it
0
.
-
Commutative: Changing the order of inputs doesn’t matter.
-
Associative: Grouping inputs in any way doesn’t matter.
-
Minterm = A⋅B‾⋅C⋅D‾
-
sum of products: Y=(A⋅B‾⋅C⋅D)+(A‾⋅B⋅C⋅D‾)+(A⋅B⋅C‾⋅D‾)
For OR(maxterm) gate
-
Identity: \( A + 0 = A \)
-
Null: \( A + 1 = 1 \)
-
Commutative: \( A + B = B + A \)
-
Associative: \( A + (B + C) = (A + B) + C \)
-
Idempotent: \( A + A = A \)
-
Distributive:
- Over AND: \( A + (B AND C) = (A + B) AND (A + C) \)
- Over OR: ( A + (B + C) = (A + B) + C )
--
Maxterm = (A‾+B+C‾+D)
-
Product of sums: Y=(A‾+B+C‾+D)⋅(A+B‾+C+D‾)⋅(A‾+B‾+C‾+D)
Prority Encoder
Definition:
A Priority Encoder is a combinational circuit that encodes the position of the highest-priority active input into a binary output.
Key Features:
-
Inputs: \( 2^n \) input lines; only one active at a time is expected.
-
Outputs: \( n \) output lines representing the binary code of the highest-priority input.
-
Priority: Higher-order inputs have precedence over lower-order inputs.
-
Enable Output: Indicates if any input is active (optional).
Logic Expressions (4-to-2 Priority Encoder):
- Y_1 = D_3 + D_2
- Y_0 = D_3 +{D_2}‾ * D_1
- Enable Output (E = D_3 + D_2 + D_1 + D_0
Applications:
1.
Interrupt Handling: Assigns priority to multiple interrupt signals in processors.
2.
Data Compression: Encodes multiple inputs into fewer bits.
3.
Memory Decoding: Selects the highest-priority address or resource.
Advantages:
- Handles multiple inputs with priority logic.
- Compresses input size efficiently.
Limitations:
- Requires additional handling if multiple inputs have the same priority.
- Extra circuitry needed for "no active input" conditions.
Causes of Delay in Circuit State Change (Low to High)
Definition:
Delays occur when a circuit element transitions from
0
(low) to
1
(high) due to physical and electrical factors.
Key Causes of Delay
1.
Propagation Delay:
- Time taken for a signal to propagate through a circuit element.
- Affects overall circuit speed.
2.
Gate Capacitance:
- Time required to charge or discharge the transistor's gate capacitance.
3.
Load Capacitance:
- Higher load capacitance slows the charging/discharging process.
4.
Resistance of Interconnects:
- Higher resistance in wires increases \( RC \) delay.
5.
Signal Rise Time:
- Time taken for the signal to rise from 10% to 90% of its final value.
6.
Threshold Voltage:
- Higher voltage thresholds cause slower transitions.
7.
Noise and Signal Integrity:
- Crosstalk, interference, or power fluctuations can distort signals.
8.
Power Supply Voltage:
- Lower voltages reduce drive strength, increasing delay.
9.
Temperature Effects:
- High temperatures slow down transistor switching.
10.
Manufacturing Variations:
- Fabrication inconsistencies can result in slower components.
11.
Clock Synchronization:
- Skew or jitter in clock signals causes timing delays in sequential circuits.
12.
Parasitic Elements:
- Unintended resistance, capacitance, or inductance contributes to delay.
Summary:
Delays result from intrinsic (e.g., propagation, capacitance) and external factors (e.g., noise, temperature). Optimizing design and materials can mitigate these delays.
