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EIOT 1 Cheat Sheet (DRAFT) by

Embedded Systems and Internet of Things

This is a draft cheat sheet. It is a work in progress and is not finished yet.

Embedded System

specia­lized computer system; specific function; combining hardware and software
Washing Machine (wash cycles, water levels), Automobile Airbag System (detect collision and deploy airbag)

Assembly language

direct control over hardware and registers
highly efficient + compact code
precise timing + real-time control
low-level device drivers; ISR routines

RISC vs. CISC

RISC
CISC
small set of simple instru­ctions
large set of complex instru­ctions
fixed-­length
variab­le-­length
one instru­ction in one clock cycle
instru­ctions take multiple cycles
software optimi­zation
hardware optimi­zation

Harvard vs. Von Neumann

Harvard
Von Neumann
modern archit­ecture based on Harvard Mark I relay based model.
ancient computer archit­ecture based on stored program computer concept
instru­ctions + data → different memory; buses
instru­ctions + data → same physical memory; common bus
an instru­ction in single cycle
two clock cycles for single instru­ction

parallel port progra­mming

control multiple data lines simult­ane­ously
send + receive data in parallel
configure + access I/O port registers
Faster data transfer

data transfer instru­ctions

Move data between registers, memory, and I/O ports
 

Microp­roc­essor vs. Microc­ont­roller

Microp­roc­essor
Microc­ont­roller
single CPU on chip
CPU, I/O, memory on chip
requires external RAM, ROM and I.O devices
all internal
genera­l-p­urpose
specific embedded applic­ations
higher processing power
moderate
higher power consum­ption
low
more expensive
cost effective

Instru­ction Set

interface between hardware and software
Controls data movement (I/O and periph­eral), arithm­etic, and logic operations
program flow control (branc­hing, looping)
Instru­ctions supported by 8051
Data Transfer Instru­ctions
MOV, MOVC, and MOVX (inter­nal­/ex­ternal, code memory)
PUSH and POP (stack)
XCH and XCHD (between accumu­lator & registers /memory)
1. Arithmetic
ADD, ADDC, SUBB, INC, and DEC; MUL AB and DIV AB (8 bit numbers)
2. Logical
AND, OR, XOR, comple­ment, rotate, NOT
ANL, ORL, XRL, CLR, CPL, RL, and RRC
3. Bit Manipu­lation
SETB, CLR, JB, JNB, and JBC
Set, clear, comple­ment, and test bits
Control Instru­ctions
Branching; subroutine calls (ACALL, LCALL), returns (RET, RETI), Boolean operat­ions, and NOP for no operation
4. Branching
SJMP, LJMP, DJNZ
Jump, call, return, and loop control
5. Boolean
single-bit variables and carry flag
Arithmetic instru­ctions affect Carry (CY), Auxiliary Carry (AC), and Overflow (OV) flags.

Microc­ont­roller archit­ecture (8051)

1. CPU (Central Processing Unit)
8-bit (arithmetic+logical)
ALU; internal registers; program counter
2. Program Memory (ROM / Flash)
4KB; program storage (cannot be modified)
3. Data Memory (RAM)
128 bytes (tempo­rary); 4 register banks (8 registers each)
4. Input/­Output (I/O) Ports
four 8 bit (32 pins); bidire­ctional
5. Timers and Counters
two 16 bit (for 8051); hardware based delay
1. Select Timer Mode
16-bit or 8-bit
2. Load Timer Register
initial value so timer overflows after desired time
3. Start Timer
set control bits (counting)
4. Wait for Overflow Flag
monitor overflow flag (TFx)
5. Stop Timer & Clear Flag
Reset for next use
6. Interrupt Control
Interrupt - tempor­arily halt normal execution.
execute a specific interrupt service routine (ISR)
immediate response to external or internal events; real-time
7. Serial Commun­ication Interfaces
8. Clock / Oscillator
9. Power Supply and Reset Circuit
Program Status word
8-bit wide; 6 active flags; 2 user-d­efined bits
Accumu­lator
Stores operands and results of arithmetic and logic operations
Program Counter
holds address of next instru­ction to be executed
Stack Pointer
point to top of the stack
Special Function Registers 8051
control + configure periph­erals (/O ports, timers­/co­unters, serial commun­ica­tion, and interrupts)
CPU control and status information
direct access to hardware
special operations beyond general purpose
Data Pointer
16-bit user-a­cce­ssible register; access external memory
In the RAM, only one register bank can be active at a time

fig. 1

  

Addressing modes

Immediate Addressing
transfers data (8 bit constant) directly to destination
MOV A, #6AH
instructions are 2 bytes long, execute in 1 cycle
Register Addressing
specifies the memory address
MOV A, 04H
Direct Addressing
uses register names (R0–R7)
MOV A, R4
1 byte and 1 cycle
Indirect Addressing
address of data inside a register
MOV A, @R0
Indexed Addressing
accessing data from program memory using MOVC
MOVC A, @A+DPTR
2 machine cycles

Timers and counters

Timer0, Timer1
16 bit; accessed using two 8-bit registers: THx and TLx.
internal clock → derived from external crystal oscillator
timer clock frequency is 1/12th of the crystal frequency (machine cycle frequency)
TMOD register
8-bit register; select timer mode + operations
lower 4 → Timer0; upper 4 → Timer1
GATE bit → enables timer (when external interrupt pin + run control bit active)
C/T bit → selects between timer (internal clock) and counter mode (external pulses)
Modes
Mode 0 - 13-bit timer; 8 bits of THx and 5 bits of TLx
Mode 1 - 16-bit timer; THx and TLx form a full 16-bit counter.
Mode 2 - 8-bit auto-r­eload; TLx reloads automa­tically from THx after overflow.
Mode 3 - splits Timer0 into two 8-bit timers; Timer1 stops functi­oning
TCON register
controls timer operation and contains overflow flags (TF0, TF1) and run control bits (TR0, TR1).

fig. 2

fig. 3