This is a draft cheat sheet. It is a work in progress and is not finished yet.
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N-stage pipeline
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P2 is a 7-stage pipelined processor with the clock cycle time of 200ps. If you are given a program with 1000 instructions without any pipeline hazards, calculate the execution times on P1 and P2 P2=(7*200ps)+(200ps*999 inits)
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Hazards
Structure Hazards |
A required resource is busy |
Data Hazards |
Need to wait for previous instruction to complete its data read/write |
Control Hazard |
Deciding on control action depends on previous instruction |
Pipeline stages
Five stages:
1. IF: Instruction fetch from memory
2. ID: Instruction decode & register read
3. EX: Execute operation or calculate address
4. MEM: Access memory operand
5. WB: Write result back to register |
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