Cheatography
https://cheatography.com
cocotb is a COroutine based COsimulation TestBench environment for verifying VHDL/Verilog RTL using Python.
This is a draft cheat sheet. It is a work in progress and is not finished yet.
Enviroment
Make SIM=ghdl TOPLEVE_LANG=vhdl SIM_ARGS=--wave=waveform.ghw |
@cocotb.test()
def name_test(dut,...)
"""Description:"""
raise TestFailure("text")
dut._log.info("Ok!")
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@cocotb.coroutine
List of triggers |
result = yield [tout_trigger, RisingEdge(dut.ready)] |
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Simulator Triggers
cocotb.triggers.Edge(signal) |
Fires on any value change of signal. |
cocotb.triggers.RisingEdge(signal) |
Fires on the rising edge of signal, on a transition from 0 to 1. |
cocotb.triggers.FallingEdge(signal) |
Fires on the rising edge of signal, on a transition from 0 to 1. |
cocotb.triggers.ClockCycles(signal, num_cycles, rising=True)[source] |
Fires after num_cycles transitions of signal from 0 to 1. |
Timing
cocotb.triggers.Timer(time_ps, units=None)[source] |
cocotb.fork(Clock(dut.c, 10, 'us').start(start_high=False)) |
units (str or None, optional) – One of None, 'fs', 'ps', 'ns', 'us', 'ms', 'sec'.
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