Arithmetic Instructions
Mnemonic 
Description 
Operation 
Flags 
Clocks^{(1)} 
ADD Rd, Rr 
Add without Carry 
Rd ← Rd + Rr 
Z,C,N,V,S,H 
1  1  1 1 
ADC Rd, Rr 
Add with Carry 
Rd ← Rd + Rr + C 
Z,C,N,V,S,H 
1  1  1 1 
ADIW Rd, K 
Add Immediate to Word 
Rd ← Rd+1:Rd + K 
Z,C,N,V,S 
2  2  2  N/A 
SUB Rd, Rr 
Subtract without Carry 
Rd ← Rd  Rr 
Z,C,N,V,S,H 
1  1  1 1 
SUBI Rd, K 
Subtract Immediate 
Rd ← Rd  K 
Z,C,N,V,S,H 
1  1  1 1 
SBC Rd, Rr 
Subtract with Carry 
Rd ← Rd  Rr  C 
Z,C,N,V,S,H 
1  1  1 1 
SBCI Rd, K 
Subtract Immediate with Carry 
Rd ← Rd  K  C 
Z,C,N,V,S,H 
1  1  1 1 
SBIW Rd, K 
Subtract Immediate from Word 
Rd+1:Rd ← Rd+1:Rd  K 
Z,C,N,V,S 
2  2  2  N/A 
NEG Rd 
Two’s Complement 
Rd ← $00  Rd 
Z,C,N,V,S,H 
1  1  1 1 
INC Rd 
Increment 
Rd ← Rd + 1 
Z,N,V,S 
1  1  1 1 
DEC Rd 
Decrement 
Rd ← Rd  1 
Z,N,V,S 
1  1  1 1 
MUL Rd,Rr 
Multiply Unsigned 
R1:R0 ← Rd x Rr (UU) 
Z,C 
2  2  2  N/A 
MULS Rd,Rr 
Multiply Signed 
R1:R0 ← Rd x Rr (SS) 
Z,C 
2  2  2  N/A 
MULSU Rd,Rr 
Multiply Signed with Unsigned 
R1:R0 ← Rd x Rr (SU) 
Z,C 
2  2  2  N/A 
FMUL Rd,Rr 
Fractional Multiply Unsigned 
R1:R0 ← Rd x Rr<<1 (UU) 
Z,C 
2  2  2  N/A 
FMULS Rd,Rr 
Fractional Multiply Signed 
R1:R0 ← Rd x Rr<<1 (SS) 
Z,C 
2  2  2  N/A 
FMULSU Rd,Rr 
Fractional Multiply Signed with Unsigned 
R1:R0 ← Rd x Rr<<1 (SU) 
Z,C 
2  2  2  N/A 
1. Number of clocks in AVR 8bit CPU version (AVR  AVRxm  AVRxt  AVRrc)
