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% Document Info
\author{AlexHoratio (Horatio)}
\pdfinfo{
  /Title (wjec-a2-computing-unit-4-1.pdf)
  /Creator (Cheatography)
  /Author (AlexHoratio (Horatio))
  /Subject (WJEC A2 Computing Unit 4.1 Cheat Sheet)
}

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\noindent
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    {\parbox{\dimexpr\textwidth-2\fboxsep\relax}{\noindent
        \hspace*{-6pt}\includegraphics[width=5.8cm]{/web/www.cheatography.com/public/images/cheatography_logo.pdf}}
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\begin{tabulary}{11cm}{L}
    \vspace{-2pt}\large{\bf{\textcolor{DarkBackground}{\textrm{WJEC A2 Computing Unit 4.1 Cheat Sheet}}}} \\
    \normalsize{by \textcolor{DarkBackground}{AlexHoratio (Horatio)} via \textcolor{DarkBackground}{\uline{cheatography.com/21127/cs/16076/}}}
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\noindent
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  \mymulticolumn{2}{p{5.377cm}}{\bf\textcolor{white}{Cheatographer}}  \\
  \vspace{-2pt}AlexHoratio (Horatio) \\
  \uline{cheatography.com/horatio} \\
        \uline{\seqsplit{alexhoratiogamedev}.blogspot.com}
  \end{tabulary}
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  \mymulticolumn{1}{p{5.377cm}}{\bf\textcolor{white}{Cheat Sheet}}  \\
   \vspace{-2pt}Published 12th June, 2018.\\
   Updated 12th June, 2018.\\
   Page {\thepage} of \pageref{LastPage}.
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  \mymulticolumn{1}{p{5.377cm}}{\bf\textcolor{white}{Sponsor}}  \\
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  \vspace{-5pt}
  %\includegraphics[width=48px,height=48px]{dave.jpeg}
  Measure your website readability!\\
  www.readability-score.com
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\begin{multicols*}{3}

\begin{tabularx}{5.377cm}{X}
\SetRowColor{DarkBackground}
\mymulticolumn{1}{x{5.377cm}}{\bf\textcolor{white}{Network Hardware}}  \tn
% Row 0
\SetRowColor{LightBackground}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Network Interface Card (NIC)}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}{\bf{1.}} NICs take data that the computer sends it and transmits it through any connected network cable via the appropriate protocol.  \{\{nl\}\} {\bf{2.}} The most popular one is {\bf{Ethernet}}, or for wireless the {\bf{802.11 protocol}}..} \tn 
% Row Count 6 (+ 6)
% Row 1
\SetRowColor{white}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Hub}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}{\bf{1.}} Allows more than one computer to be connected in a network by connecting them all to a hub. \{\{nl\}\} {\bf{2.}} If a cable breaks, it only affects the computer connected to the hub through that cable. \{\{nl\}\} {\bf{3.}} This is generally very {\bf{slow for large networks}}, since the more traffic that is generated means the more work that the hub has to do. \{\{nl\}\} {\bf{4.}} When a hub receives a packet, it transmits the packet to all connected ports.} \tn 
% Row Count 17 (+ 11)
% Row 2
\SetRowColor{LightBackground}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Switch}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}{\bf{1.}} Unlike hubs, a switch can route packets from one port to another. This is known as {\bf{routing}}. \{\{nl\}\} {\bf{2.}} Switches hold a {\bf{MAC address table}} to determine which computer is connected to which port.} \tn 
% Row Count 23 (+ 6)
% Row 3
\SetRowColor{white}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Router}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}{\bf{1.}} Routers perform the same as switches, except instead of using MAC addresses to determine where to send packets they use IP addresses.  \{\{nl\}\} {\bf{2.}} These are used for {\bf{WANs}} or very large networks.} \tn 
% Row Count 29 (+ 6)
% Row 4
\SetRowColor{LightBackground}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Wireless Interface Card (WIC)}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}{\bf{1.}} This connects to a {\bf{WAP}} or {\bf{W}}ireless {\bf{A}}ccess {\bf{P}}oint. \{\{nl\}\} {\bf{2.}} Most WICs use the 802.11 protocol to communicate with the WAP, in combination with security protocols such as {\bf{WEP}} or {\bf{WPA2}}.} \tn 
% Row Count 35 (+ 6)
\hhline{>{\arrayrulecolor{DarkBackground}}-}
\end{tabularx}
\par\addvspace{1.3em}

\begin{tabularx}{5.377cm}{X}
\SetRowColor{DarkBackground}
\mymulticolumn{1}{x{5.377cm}}{\bf\textcolor{white}{Cache}}  \tn
% Row 0
\SetRowColor{LightBackground}
\mymulticolumn{1}{x{5.377cm}}{{\bf{RAM Cache}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}Also known as {\bf{L2 or L3 cache}}, this is a memory chip between the CPU and main memory where small sections of data are stored.\{\{nl\}\} These are {\bf{extremely fast}} since they are small and close to the CPU.} \tn 
% Row Count 6 (+ 6)
% Row 1
\SetRowColor{white}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Disk Cache}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}This is a section of memory between the CPU and the disk where data can be temporarily stored before being transferred to RAM.} \tn 
% Row Count 10 (+ 4)
\hhline{>{\arrayrulecolor{DarkBackground}}-}
\end{tabularx}
\par\addvspace{1.3em}

\begin{tabularx}{5.377cm}{X}
\SetRowColor{DarkBackground}
\mymulticolumn{1}{x{5.377cm}}{\bf\textcolor{white}{Types of Network}}  \tn
% Row 0
\SetRowColor{LightBackground}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Local Area Network (LAN)}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}Connected locally, usually on the same site.} \tn 
% Row Count 2 (+ 2)
% Row 1
\SetRowColor{white}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Wide Area Network (WAN)}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}Connected via satellite links or any other method, may be spread out across towns or countries} \tn 
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% Row 2
\SetRowColor{LightBackground}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Storage Area Network (SAN)}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}A dedicated network for large scale data storage. Usually provides a disc array of high capacity and performance.} \tn 
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% Row 3
\SetRowColor{white}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Metropolitan Area Network (MAN)}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}Networks that provide WAN services in a city.} \tn 
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% Row 4
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\mymulticolumn{1}{x{5.377cm}}{{\bf{Personal Area Network (PAN)}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}Links personal devices such as phones.} \tn 
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\begin{tabularx}{5.377cm}{X}
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\mymulticolumn{1}{x{5.377cm}}{\bf\textcolor{white}{Harvard Architecture}}  \tn
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\mymulticolumn{1}{p{5.377cm}}{\vspace{1px}\centerline{\includegraphics[width=5.1cm]{/web/www.cheatography.com/public/uploads/horatio_1528793790_Screenshot from 2018-06-12 09-55-25.png}}} \tn 
\hhline{>{\arrayrulecolor{DarkBackground}}-}
\SetRowColor{LightBackground}
\mymulticolumn{1}{x{5.377cm}}{In the {\bf{Harvard Architecture}}, data and instructions are stored seperately and accessed via separate buses. The Harvard Architecture is generally used by {\bf{RISC}} processors.}  \tn 
\hhline{>{\arrayrulecolor{DarkBackground}}-}
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\begin{tabularx}{5.377cm}{X}
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\mymulticolumn{1}{x{5.377cm}}{\bf\textcolor{white}{Parallel Processing}}  \tn
% Row 0
\SetRowColor{LightBackground}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Parallel Processing}} involves setting two or more processors to perform a single task. The task is split into {\bf{threads}} which can run concurrently.} \tn 
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% Row 1
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\mymulticolumn{1}{x{5.377cm}}{{\bf{Advantages}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}{\bf{1.}} More instructions can be processed in a given amount of time since they can be executed concurrently. \{\{nl\}\} {\bf{2.}} Tasks can be shared to reduce bottlenecks} \tn 
% Row Count 9 (+ 5)
% Row 2
\SetRowColor{LightBackground}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Disadvantages}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}{\bf{1.}} It is difficult to write programs for multi-core processors. \{\{nl\}\} {\bf{2.}} Results from different processors need to be combined at the end of the program which may take more time.  \{\{nl\}\} {\bf{3.}} Not all tasks can be parallelized. \{\{nl\}\} {\bf{4.}} Concurrency may introduce new software bugs.} \tn 
% Row Count 17 (+ 8)
\hhline{>{\arrayrulecolor{DarkBackground}}-}
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\begin{tabularx}{5.377cm}{X}
\SetRowColor{DarkBackground}
\mymulticolumn{1}{x{5.377cm}}{\bf\textcolor{white}{Fetch-Execute Cycle}}  \tn
% Row 0
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\mymulticolumn{1}{x{5.377cm}}{{\bf{Fetch}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}The processor sends the address held in the {\bf{PC}} to the address bus. The data is sent back to the {\bf{CIR}} and the {\bf{PC}} is incremented.} \tn 
% Row Count 4 (+ 4)
% Row 1
\SetRowColor{white}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Execute}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}The processor runs the instruction in the CIR. It then {\bf{fetches}} the next instruction.} \tn 
% Row Count 7 (+ 3)
\hhline{>{\arrayrulecolor{DarkBackground}}-}
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\begin{tabularx}{5.377cm}{X}
\SetRowColor{DarkBackground}
\mymulticolumn{1}{x{5.377cm}}{\bf\textcolor{white}{Primary Storage}}  \tn
% Row 0
\SetRowColor{LightBackground}
\mymulticolumn{1}{x{5.377cm}}{{\bf{RAM (Random Access Memory)}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}RAM is {\bf{volatile}} and relatively slow compared to other methods of primary storage. It is useful for storing parts of programs while they are being run.} \tn 
% Row Count 5 (+ 5)
% Row 1
\SetRowColor{white}
\mymulticolumn{1}{x{5.377cm}}{{\bf{ROM (Read Only Memory)}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}ROM is {\bf{not volatile}} and read-only. This means that once data has been programmed into it, it cannot be overwritten.} \tn 
% Row Count 9 (+ 4)
\hhline{>{\arrayrulecolor{DarkBackground}}-}
\end{tabularx}
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\begin{tabularx}{5.377cm}{X}
\SetRowColor{DarkBackground}
\mymulticolumn{1}{x{5.377cm}}{\bf\textcolor{white}{Graphics Processing Unit}}  \tn
% Row 0
\SetRowColor{LightBackground}
\mymulticolumn{1}{x{5.377cm}}{{\bf{GPUs}} are able to run a single instruction on multiple pieces of data in parallel. This is known as {\bf{SIMD}} - {\bf{S}}ingle {\bf{I}}nstruction {\bf{M}}ultiple {\bf{D}}ata.} \tn 
% Row Count 4 (+ 4)
% Row 1
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\mymulticolumn{1}{x{5.377cm}}{GPUs are frequently used for processing screen data, since operations can be performed on each pixel in parallel.} \tn 
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\hhline{>{\arrayrulecolor{DarkBackground}}-}
\end{tabularx}
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\begin{tabularx}{5.377cm}{X}
\SetRowColor{DarkBackground}
\mymulticolumn{1}{x{5.377cm}}{\bf\textcolor{white}{Factors Affecting Performance}}  \tn
% Row 0
\SetRowColor{LightBackground}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Clock Speed}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}This is how many {\bf{ticks per second}} the CPU is able to perform.} \tn 
% Row Count 3 (+ 3)
% Row 1
\SetRowColor{white}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Bus Width}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}This determines how much data can be transferred along each bus in a single tick.} \tn 
% Row Count 6 (+ 3)
% Row 2
\SetRowColor{LightBackground}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Word Length}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}How many bits can be processed at a time. This is usually either {\bf{32}} or {\bf{64}} bits.} \tn 
% Row Count 9 (+ 3)
% Row 3
\SetRowColor{white}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Multiple Cores}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}A multi-core CPU will be able to run two different instructions at the same time. This is useful for tasks that can be {\bf{parallelized}}.} \tn 
% Row Count 13 (+ 4)
% Row 4
\SetRowColor{LightBackground}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Cache Memory}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}Frequently used information can be placed into a temporary area of memory close to the CPU. This is much {\bf{faster}} to read from.} \tn 
% Row Count 17 (+ 4)
\hhline{>{\arrayrulecolor{DarkBackground}}-}
\end{tabularx}
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\begin{tabularx}{5.377cm}{X}
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\mymulticolumn{1}{x{5.377cm}}{\bf\textcolor{white}{Network Models}}  \tn
% Row 0
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\mymulticolumn{1}{x{5.377cm}}{{\bf{Client-Server}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}This is where the client frequently requests data from a central entity, the server. This is the most common type of network since it seperates functions, such as storage or printing.} \tn 
% Row Count 5 (+ 5)
% Row 1
\SetRowColor{white}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Peer-to-Peer}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}This is where every computer is a client. This is cheaper to implement and also useful for sharing files frequently between computers.} \tn 
% Row Count 9 (+ 4)
\hhline{>{\arrayrulecolor{DarkBackground}}-}
\end{tabularx}
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\begin{tabularx}{5.377cm}{x{2.4885 cm} x{2.4885 cm} }
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\mymulticolumn{2}{x{5.377cm}}{\bf\textcolor{white}{Networks}}  \tn
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{\bf{Advantages}}\{\{ac\}\} & {\bf{Disadvantages}}\{\{ac\}\} \tn 
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Hardware such as {\bf{printers}} can be shared & {\bf{Viruses}} can be spread across a network to all computers \tn 
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Software can be shared & {\bf{Hackers}} may be able to access a network \tn 
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Data can be shared, e.g from a {\bf{file server}} & {\bf{Network failure}} means that nobody can use their computer \tn 
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Computers may {\bf{communicate}} with each other via messaging & Networks may be {\bf{slower}} than standalone computers \tn 
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 & Complex cabling may be {\bf{expensive}} to install \tn 
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\hhline{>{\arrayrulecolor{DarkBackground}}--}
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\begin{tabularx}{5.377cm}{X}
\SetRowColor{DarkBackground}
\mymulticolumn{1}{x{5.377cm}}{\bf\textcolor{white}{Amdahl's Law}}  \tn
\SetRowColor{LightBackground}
\mymulticolumn{1}{p{5.377cm}}{\vspace{1px}\centerline{\includegraphics[width=5.1cm]{/web/www.cheatography.com/public/uploads/horatio_1528795346_Screenshot from 2018-06-12 10-21-14.png}}} \tn 
\hhline{>{\arrayrulecolor{DarkBackground}}-}
\SetRowColor{LightBackground}
\mymulticolumn{1}{x{5.377cm}}{This is where {\bf{T(n)}} is the time taken on {\bf{n}} threads and {\bf{B}} is the fraction of the algorithm that must be sequential.}  \tn 
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\end{tabularx}
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\begin{tabularx}{5.377cm}{X}
\SetRowColor{DarkBackground}
\mymulticolumn{1}{x{5.377cm}}{\bf\textcolor{white}{CPU Components}}  \tn
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\mymulticolumn{1}{x{5.377cm}}{{\bf{ALU (Arithmetic and Logic Unit)}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}Carries out mathematical and logical functions. It is sent an {\bf{opcode}} and an {\bf{operand}} and carries out the required process.} \tn 
% Row Count 4 (+ 4)
% Row 1
\SetRowColor{white}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Control Unit}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}Supervises the {\bf{fetch-execute cycle}}. The control unit also {\bf{decodes instructions}}.} \tn 
% Row Count 7 (+ 3)
\hhline{>{\arrayrulecolor{DarkBackground}}-}
\end{tabularx}
\par\addvspace{1.3em}

\begin{tabularx}{5.377cm}{X}
\SetRowColor{DarkBackground}
\mymulticolumn{1}{x{5.377cm}}{\bf\textcolor{white}{Buses}}  \tn
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\SetRowColor{LightBackground}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Buses}} are groups of parallel wires which connect the processor to I/O controllers or memory. There are {\bf{three}} types of bus:} \tn 
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% Row 1
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\mymulticolumn{1}{x{5.377cm}}{{\bf{Data Bus}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}The data bus is {\bf{bidirectional}} and carries data between the CPU and the main memory. The {\bf{width}} of the data bus is usually the same as the {\bf{CPU word size}}, so either 32 or 64 are common.} \tn 
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% Row 2
\SetRowColor{LightBackground}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Address Bus}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}This bus only goes from the processor to memory. This is used by the processor to retrieve data from memory. The address bus carries the memory address of the {\bf{next instruction or data item}} to be received through the {\bf{data bus}}.} \tn 
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% Row 3
\SetRowColor{white}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Control Bus}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}This is a {\bf{bidirectional}} bus that sends control signals to the registers, data and address bus. This helps to ensure that everything is kept in sync.} \tn 
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\hhline{>{\arrayrulecolor{DarkBackground}}-}
\end{tabularx}
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\begin{tabularx}{5.377cm}{X}
\SetRowColor{DarkBackground}
\mymulticolumn{1}{x{5.377cm}}{\bf\textcolor{white}{von Neumann Architecture}}  \tn
\SetRowColor{LightBackground}
\mymulticolumn{1}{p{5.377cm}}{\vspace{1px}\centerline{\includegraphics[width=5.1cm]{/web/www.cheatography.com/public/uploads/horatio_1528793707_Screenshot from 2018-06-12 09-53-13.png}}} \tn 
\hhline{>{\arrayrulecolor{DarkBackground}}-}
\SetRowColor{LightBackground}
\mymulticolumn{1}{x{5.377cm}}{The {\bf{von Neumann architecture}} describes a computer with one control unit that sequentially works through instructions. Instructions and memory are bundled together. This means that instructions can't be fetched while data is being sent along the bus, causing the {\bf{von Neumann Bottleneck}}}  \tn 
\hhline{>{\arrayrulecolor{DarkBackground}}-}
\end{tabularx}
\par\addvspace{1.3em}

\begin{tabularx}{5.377cm}{X}
\SetRowColor{DarkBackground}
\mymulticolumn{1}{x{5.377cm}}{\bf\textcolor{white}{Input and Output Devices}}  \tn
% Row 0
\SetRowColor{LightBackground}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Optical Character Recognition (OCR)}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}This converts printed(often hand-written) media into editable text documents via scanning.} \tn 
% Row Count 3 (+ 3)
% Row 1
\SetRowColor{white}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Optical Mark Recognition (OMR)}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}The computer reads selections from a predefined form. This is often used for multiple-choice tests.} \tn 
% Row Count 7 (+ 4)
% Row 2
\SetRowColor{LightBackground}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Magnetic Ink Recognition (MICR)}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}A computer uses magnets to read data from a strip of semi-magnetic material. This is used most commonly for cheques since the reader can be very expensive.} \tn 
% Row Count 12 (+ 5)
% Row 3
\SetRowColor{white}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Touch Screens}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}There are two types of touch screen. \{\{nl\}\} 1. {\bf{Resistive touch screens}} are made up of two thin transparent sheets that transmit a signal when they touch. \{\{nl\}\} 2. {\bf{Capacitive touch screens}} are more common and use the fact that the human body conducts electricity to determine when a touch has occurred.} \tn 
% Row Count 20 (+ 8)
% Row 4
\SetRowColor{LightBackground}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Voice Input}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}The computer detects commands spoken by the user into a microphone.} \tn 
% Row Count 23 (+ 3)
% Row 5
\SetRowColor{white}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Vocabulary Dictation}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}The computer attempts to detect all words spoken by the user. This is used frequently by people with RSI.} \tn 
% Row Count 27 (+ 4)
\hhline{>{\arrayrulecolor{DarkBackground}}-}
\end{tabularx}
\par\addvspace{1.3em}

\begin{tabularx}{5.377cm}{X}
\SetRowColor{DarkBackground}
\mymulticolumn{1}{x{5.377cm}}{\bf\textcolor{white}{I/O Controllers}}  \tn
% Row 0
\SetRowColor{LightBackground}
\mymulticolumn{1}{x{5.377cm}}{{\bf{I/O Controllers}} are able to translate signals from external devices into something understandable by the CPU.} \tn 
% Row Count 3 (+ 3)
% Row 1
\SetRowColor{white}
\mymulticolumn{1}{x{5.377cm}}{Also, I/O Controllers will {\bf{buffer data}} that is sent between the processor and the external device so that the processor does not have to wait.} \tn 
% Row Count 6 (+ 3)
\hhline{>{\arrayrulecolor{DarkBackground}}-}
\end{tabularx}
\par\addvspace{1.3em}

\begin{tabularx}{5.377cm}{X}
\SetRowColor{DarkBackground}
\mymulticolumn{1}{x{5.377cm}}{\bf\textcolor{white}{Cloud Storage}}  \tn
% Row 0
\SetRowColor{LightBackground}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Cloud storage}} is off-site storage that is accessible anywhere and usually provided by a third party company.} \tn 
% Row Count 3 (+ 3)
% Row 1
\SetRowColor{white}
\mymulticolumn{1}{x{5.377cm}}{This is useful for a few reasons: \{\{nl\}\} {\bf{1.}} Removes the need to install and upgrade software \{\{nl\}\} {\bf{2.}} Removes the need to hire specialist staff \{\{nl\}\} {\bf{3.}} Removes the need to back up data.} \tn 
% Row Count 7 (+ 4)
% Row 2
\SetRowColor{LightBackground}
\mymulticolumn{1}{x{5.377cm}}{However, there are drawbacks: \{\{nl\}\} {\bf{1.}} Handing control of data to another party may be risky \{\{nl\}\} {\bf{2.}} Risk of losing access to the service and having no means to recover} \tn 
% Row Count 11 (+ 4)
\hhline{>{\arrayrulecolor{DarkBackground}}-}
\end{tabularx}
\par\addvspace{1.3em}

\begin{tabularx}{5.377cm}{X}
\SetRowColor{DarkBackground}
\mymulticolumn{1}{x{5.377cm}}{\bf\textcolor{white}{Registers}}  \tn
% Row 0
\SetRowColor{LightBackground}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Registers}} are located in the CPU and hold only a few bits of data at a time. However, they are very {\bf{fast}} to access.\{\{nl\}\} There are many types of registers in the CPU:} \tn 
% Row Count 4 (+ 4)
% Row 1
\SetRowColor{white}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Status Register}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}This keeps track of the status of many parts of the computer.} \tn 
% Row Count 7 (+ 3)
% Row 2
\SetRowColor{LightBackground}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Interrupt Register}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}This stores details of any interrupt signals sent to the processor. If a bit is set in the interrupt register, the CPU must respond depending on its severity.} \tn 
% Row Count 12 (+ 5)
% Row 3
\SetRowColor{white}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Current Instruction Register (CIR)}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}Stores the currently executed instruction} \tn 
% Row Count 14 (+ 2)
% Row 4
\SetRowColor{LightBackground}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Program Counter (PC)}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}Stores the memory location of the next instruction} \tn 
% Row Count 17 (+ 3)
% Row 5
\SetRowColor{white}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Memory Buffer Register (MBR)}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}Holds the data that has just been transferred between memory} \tn 
% Row Count 20 (+ 3)
% Row 6
\SetRowColor{LightBackground}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Accumulator (ACC)}}} \tn 
\mymulticolumn{1}{x{5.377cm}}{\hspace*{6 px}\rule{2px}{6px}\hspace*{6 px}Stores the results of the {\bf{ALU}}} \tn 
% Row Count 22 (+ 2)
\hhline{>{\arrayrulecolor{DarkBackground}}-}
\end{tabularx}
\par\addvspace{1.3em}

\begin{tabularx}{5.377cm}{X}
\SetRowColor{DarkBackground}
\mymulticolumn{1}{x{5.377cm}}{\bf\textcolor{white}{Addressable Memory}}  \tn
% Row 0
\SetRowColor{LightBackground}
\mymulticolumn{1}{x{5.377cm}}{{\bf{Memory}} is made up of a number of uniquely identifiable {\bf{addressable cells}}.} \tn 
% Row Count 2 (+ 2)
% Row 1
\SetRowColor{white}
\mymulticolumn{1}{x{5.377cm}}{Memory is organized systematically such that data that is related to one process is stored in one {\bf{block}}. This speeds up the time to access memory, since the computer has a vague idea of where it is.} \tn 
% Row Count 7 (+ 5)
% Row 2
\SetRowColor{LightBackground}
\mymulticolumn{1}{x{5.377cm}}{A {\bf{memory map}} can be created to show which programs are stored at which address.} \tn 
% Row Count 9 (+ 2)
\hhline{>{\arrayrulecolor{DarkBackground}}-}
\end{tabularx}
\par\addvspace{1.3em}


% That's all folks
\end{multicols*}

\end{document}