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    \vspace{-2pt}\large{\bf{\textcolor{DarkBackground}{\textrm{ComputerArchitectureCSCI2020 Cheat Sheet}}}} \\
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\begin{tabularx}{3.833cm}{X}
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\mymulticolumn{1}{x{3.833cm}}{\bf\textcolor{white}{CSCI 2020 Computer Architecture}}  \tn
\SetRowColor{white}
\mymulticolumn{1}{x{3.833cm}}{{\bf{Basic binary math and logic}} \newline % Row Count 1 (+ 1)
Binary numbers operate in base 2, where the only digits are `0` and `1`. They are fundamental in digital systems, logic design, and computing. \newline % Row Count 4 (+ 3)
1. {\bf{Binary Arithmetic:}} {\bf{Addition:}} Binary addition is similar to decimal addition, with the rules:  \newline % Row Count 7 (+ 3)
2. {\bf{Binary Subtraction}}:  {\bf{two's complement(invert bits add 1)}} of what is subtracting, add what is being taken from and discard carry \newline % Row Count 10 (+ 3)
{\bf{Logical Operations:}} \newline % Row Count 11 (+ 1)
- {\bf{AND (`A * B`)}}: Outputs `1` only if both inputs are `1` \newline % Row Count 13 (+ 2)
- {\bf{OR (`A + B`)}}: Outputs `1` if at least one input is `1`. \newline % Row Count 15 (+ 2)
- {\bf{XOR (`A ⊕ B`)}}: Outputs `1` if the inputs are different. \newline % Row Count 17 (+ 2)
- {\bf{NOT (`¬A`)}}: Inverts the input. \newline % Row Count 18 (+ 1)
- {\bf{NAND (`¬(A * B)`)}}:  Outputs `1` unless {\bf{both inputs}} are `1`. \newline % Row Count 20 (+ 2)
- {\bf{NOR (`¬(A + B)`)}}:  Outputs `1` only if {\bf{both inputs}} are `0`. \newline % Row Count 22 (+ 2)
- {\bf{XNOR (`¬(A ⊕ B)`)}}:  Outputs `1` if the {\bf{inputs are the same}}. \newline % Row Count 24 (+ 2)
- {\bf{Implication (`A → B`)}}:  Outputs `1` unless `A = 1` and `B = 0`. \newline % Row Count 26 (+ 2)
- {\bf{Equivalence (`A ↔ B`)}}:  Outputs `1` if {\bf{A and B are equal}}. Equivalent to XNOR. \newline % Row Count 28 (+ 2)
Total bit Combinations = 2\textasciicircum{}n\textasciicircum{}  \newline % Row Count 29 (+ 1)
{\bf{Dec → Hex}}       | Divide by 16, use remainders as hex digits.                 | 156 (dec)      | 9C (hex) \newline % Row Count 32 (+ 3)
} \tn 
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\mymulticolumn{1}{x{3.833cm}}{\bf\textcolor{white}{CSCI 2020 Computer Architecture (cont)}}  \tn
\SetRowColor{white}
\mymulticolumn{1}{x{3.833cm}}{{\bf{Hex → Dec}}      | Multiply digits by 16\textasciicircum{}n, sum the results.                   | 1A3 (hex)      | 419 (dec) \newline % Row Count 3 (+ 3)
{\bf{Bin → Dec}}       | Multiply bits by 2\textasciicircum{}n, sum the results.                      | 1101 (bin)     | 13 (dec) \newline % Row Count 6 (+ 3)
{\bf{Dec → Oct}}       | Divide by 8, use remainders as octal digits.                | 125 (dec)      | 175 (oct) \newline % Row Count 9 (+ 3)
{\bf{Bin → Oct }}      | Group binary into 3 bits, convert each group to octal.      | 110101 (bin)   | 65 (oct) \newline % Row Count 12 (+ 3)
{\bf{Sign Representation}}  MSB(the front of bit): `0` (positive), `1` (negative)  Negative: Invert and add 1 | | {\bf{Arithmetic}} | Complex | Simplified (no separate subtraction) | | {\bf{Range (4-bit)}} | (signed Magnitude(\textbackslash{}( -7 \textbackslash{}) to \textbackslash{}( +7 \textbackslash{}) | (two's complement)\textbackslash{}( -8 \textbackslash{}) to \textbackslash{}( +7 \textbackslash{}) |% Row Count 18 (+ 6)
} \tn 
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\begin{tabularx}{3.833cm}{X}
\SetRowColor{DarkBackground}
\mymulticolumn{1}{x{3.833cm}}{\bf\textcolor{white}{Combinational Logic}}  \tn
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\mymulticolumn{1}{x{3.833cm}}{{\bf{Combinational logic}} \newline % Row Count 1 (+ 1)
 {\bf{Definition}} \newline % Row Count 2 (+ 1)
- {\bf{Combinational Circuit}}: Output depends only on current inputs; no memory. \newline % Row Count 4 (+ 2)
- {\bf{Sequential Circuit}}: Output depends on current inputs and past states (memory) \newline % Row Count 6 (+ 2)
 {\bf{Key Differences}} \newline % Row Count 7 (+ 1)
| Feature              | Combinational Circuit          | Sequential Circuit            | \newline % Row Count 9 (+ 2)
|-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-|-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}--|-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-| \newline % Row Count 11 (+ 2)
| {\bf{Output Dependency}} | Current inputs only            | Current inputs + past states  | \newline % Row Count 13 (+ 2)
| {\bf{Memory}}           | No memory                     | Has memory (e.g., flip-flops) | \newline % Row Count 15 (+ 2)
| {\bf{Feedback}}         | No feedback loop              | Includes feedback loop        | \newline % Row Count 17 (+ 2)
| {\bf{Clock Signal}}     | Not required                  | Requires a clock signal       | \newline % Row Count 19 (+ 2)
| {\bf{Time Dependency}}  | Outputs appear immediately    | Outputs depend on clock cycles | \newline % Row Count 21 (+ 2)
 {\bf{Examples}} \newline % Row Count 22 (+ 1)
- {\bf{Combinational Circuit}}: \newline % Row Count 23 (+ 1)
  - Half Adder: Adds two inputs, outputs Sum = \textbackslash{}( A XOR B ), Carry = \textbackslash{}( A AND B ). \newline % Row Count 25 (+ 2)
- {\bf{Sequential Circuit}}: \newline % Row Count 26 (+ 1)
  - D Flip-Flop: Stores 1 bit of data; updates on clock edge. \newline % Row Count 28 (+ 2)
 {\bf{Applications}} \newline % Row Count 29 (+ 1)
- {\bf{Combinational Circuits}}: \newline % Row Count 30 (+ 1)
} \tn 
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\mymulticolumn{1}{x{3.833cm}}{\bf\textcolor{white}{Combinational Logic (cont)}}  \tn
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\mymulticolumn{1}{x{3.833cm}}{  - Adders, multiplexers, encoders, decoders. \newline % Row Count 1 (+ 1)
- {\bf{Sequential Circuits}}: \newline % Row Count 2 (+ 1)
  - Counters, shift registers, memory units. \newline % Row Count 3 (+ 1)
{\bf{Summary}} \newline % Row Count 4 (+ 1)
- {\bf{Combinational Circuits}}: \newline % Row Count 5 (+ 1)
  - Simple, stateless, used for logical operations. \newline % Row Count 7 (+ 2)
- {\bf{Sequential Circuits}}: \newline % Row Count 8 (+ 1)
  - Complex, state-based, used for time-sensitive or memory-based tasks. \newline % Row Count 10 (+ 2)
{\bf{For AND(also minterm) gates}} \newline % Row Count 11 (+ 1)
- {\bf{Identity}}: AND-ing anything with `1` keeps it the same. \newline % Row Count 13 (+ 2)
- {\bf{Null}}: AND-ing anything with `0` makes it `0`. \newline % Row Count 15 (+ 2)
- {\bf{Commutative}}: Changing the order of inputs doesn't matter. \newline % Row Count 17 (+ 2)
- {\bf{Associative}}: Grouping inputs in any way doesn't matter. \newline % Row Count 19 (+ 2)
-{\bf{Minterm}} = A⋅B‾⋅C⋅D‾ \newline % Row Count 20 (+ 1)
	- {\bf{sum of products}}: \seqsplit{Y=(A⋅B‾⋅C⋅D)+(A‾⋅B⋅C⋅D‾)+(A⋅B⋅C‾⋅D‾)} \newline % Row Count 22 (+ 2)
{\bf{For OR(maxterm) gate}} \newline % Row Count 23 (+ 1)
- {\bf{Identity}}: \textbackslash{}( A + 0 = A \textbackslash{})  \newline % Row Count 24 (+ 1)
- {\bf{Null}}: \textbackslash{}( A + 1 = 1 \textbackslash{})  \newline % Row Count 25 (+ 1)
- {\bf{Commutative}}: \textbackslash{}( A + B = B + A \textbackslash{})  \newline % Row Count 26 (+ 1)
- {\bf{Associative}}: \textbackslash{}( A + (B + C) = (A + B) + C \textbackslash{}) \newline % Row Count 28 (+ 2)
- {\bf{Idempotent}}: \textbackslash{}( A + A = A \textbackslash{})  \newline % Row Count 29 (+ 1)
- {\bf{Distributive}}:  \newline % Row Count 30 (+ 1)
} \tn 
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\mymulticolumn{1}{x{3.833cm}}{	- Over AND: \textbackslash{}( A + (B AND C) = (A + B) AND (A + C) \textbackslash{})  \newline % Row Count 2 (+ 2)
	- Over OR: ( A + (B + C) = (A + B) + C ) \newline % Row Count 3 (+ 1)
-{}- {\bf{Maxterm}} = (A‾+B+C‾+D) \newline % Row Count 4 (+ 1)
- {\bf{Product of sums}}: \seqsplit{Y=(A‾+B+C‾+D)⋅(A+B‾+C+D‾)⋅(A‾+B‾+C‾+D)} \newline % Row Count 6 (+ 2)
Prority Encoder \newline % Row Count 7 (+ 1)
{\bf{Definition}}:   \newline % Row Count 8 (+ 1)
A Priority Encoder is a combinational circuit that encodes the position of the highest-priority active input into a binary output. \newline % Row Count 11 (+ 3)
{\bf{Key Features}}: \newline % Row Count 12 (+ 1)
- {\bf{Inputs}}: \textbackslash{}( 2\textasciicircum{}n \textbackslash{}) input lines; only one active at a time is expected. \newline % Row Count 14 (+ 2)
- {\bf{Outputs}}: \textbackslash{}( n \textbackslash{}) output lines representing the binary code of the highest-priority input. \newline % Row Count 16 (+ 2)
- {\bf{Priority}}: Higher-order inputs have precedence over lower-order inputs. \newline % Row Count 18 (+ 2)
- {\bf{Enable Output}}: Indicates if any input is active (optional). \newline % Row Count 20 (+ 2)
{\bf{Logic Expressions (4-to-2 Priority Encoder)}}: \newline % Row Count 21 (+ 1)
- Y\_1 = D\_3 + D\_2  \newline % Row Count 22 (+ 1)
- Y\_0 = D\_3 +\{D\_2\}‾ * D\_1 \newline % Row Count 23 (+ 1)
- Enable Output (E  =  D\_3 + D\_2 + D\_1 + D\_0  \newline % Row Count 24 (+ 1)
{\bf{Applications}}: \newline % Row Count 25 (+ 1)
1. {\bf{Interrupt Handling}}: Assigns priority to multiple interrupt signals in processors. \newline % Row Count 27 (+ 2)
2. {\bf{Data Compression}}: Encodes multiple inputs into fewer bits. \newline % Row Count 29 (+ 2)
3. {\bf{Memory Decoding}}: Selects the highest-priority address or resource. \newline % Row Count 31 (+ 2)
} \tn 
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\mymulticolumn{1}{x{3.833cm}}{{\bf{Advantages}}: \newline % Row Count 1 (+ 1)
- Handles multiple inputs with priority logic. \newline % Row Count 2 (+ 1)
- Compresses input size efficiently. \newline % Row Count 3 (+ 1)
{\bf{Limitations}}: \newline % Row Count 4 (+ 1)
- Requires additional handling if multiple inputs have the same priority. \newline % Row Count 6 (+ 2)
- Extra circuitry needed for "no active input" conditions. \newline % Row Count 8 (+ 2)
Causes of Delay in Circuit State Change (Low to High) \newline % Row Count 10 (+ 2)
{\bf{Definition}}:   \newline % Row Count 11 (+ 1)
Delays occur when a circuit element transitions from `0` (low) to `1` (high) due to physical and electrical factors. \newline % Row Count 14 (+ 3)
{\bf{Key Causes of Delay}} \newline % Row Count 15 (+ 1)
1. {\bf{Propagation Delay}}: \newline % Row Count 16 (+ 1)
   - Time taken for a signal to propagate through a circuit element. \newline % Row Count 18 (+ 2)
   - Affects overall circuit speed. \newline % Row Count 19 (+ 1)
2. {\bf{Gate Capacitance}}: \newline % Row Count 20 (+ 1)
   - Time required to charge or discharge the transistor's gate capacitance. \newline % Row Count 22 (+ 2)
3. {\bf{Load Capacitance}}: \newline % Row Count 23 (+ 1)
   - Higher load capacitance slows the charging/discharging process. \newline % Row Count 25 (+ 2)
4. {\bf{Resistance of Interconnects}}: \newline % Row Count 26 (+ 1)
   - Higher resistance in wires increases \textbackslash{}( RC \textbackslash{}) delay. \newline % Row Count 28 (+ 2)
5. {\bf{Signal Rise Time}}: \newline % Row Count 29 (+ 1)
   - Time taken for the signal to rise from 10\% to 90\% of its final value. \newline % Row Count 31 (+ 2)
} \tn 
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\mymulticolumn{1}{x{3.833cm}}{6. {\bf{Threshold Voltage}}: \newline % Row Count 1 (+ 1)
   - Higher voltage thresholds cause slower transitions. \newline % Row Count 3 (+ 2)
7. {\bf{Noise and Signal Integrity}}: \newline % Row Count 4 (+ 1)
   - Crosstalk, interference, or power fluctuations can distort signals. \newline % Row Count 6 (+ 2)
8. {\bf{Power Supply Voltage}}: \newline % Row Count 7 (+ 1)
   - Lower voltages reduce drive strength, increasing delay. \newline % Row Count 9 (+ 2)
9. {\bf{Temperature Effects}}: \newline % Row Count 10 (+ 1)
   - High temperatures slow down transistor switching. \newline % Row Count 12 (+ 2)
10. {\bf{Manufacturing Variations}}: \newline % Row Count 13 (+ 1)
    - Fabrication inconsistencies can result in slower components. \newline % Row Count 15 (+ 2)
11. {\bf{Clock Synchronization}}: \newline % Row Count 16 (+ 1)
    - Skew or jitter in clock signals causes timing delays in sequential circuits. \newline % Row Count 18 (+ 2)
12. {\bf{Parasitic Elements}}: \newline % Row Count 19 (+ 1)
    - Unintended resistance, capacitance, or inductance contributes to delay. \newline % Row Count 21 (+ 2)
{\bf{Summary}}:   \newline % Row Count 22 (+ 1)
Delays result from intrinsic (e.g., propagation, capacitance) and external factors (e.g., noise, temperature). Optimizing design and materials can mitigate these delays.% Row Count 26 (+ 4)
} \tn 
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\mymulticolumn{1}{x{3.833cm}}{{\bf{Combinational logic}} \newline % Row Count 1 (+ 1)
 {\bf{Definition}} \newline % Row Count 2 (+ 1)
- {\bf{Combinational Circuit}}: Output depends only on current inputs; no memory. \newline % Row Count 4 (+ 2)
- {\bf{Sequential Circuit}}: Output depends on current inputs and past states (memory) \newline % Row Count 6 (+ 2)
 {\bf{Key Differences}} \newline % Row Count 7 (+ 1)
| Feature              | Combinational Circuit          | Sequential Circuit            | \newline % Row Count 9 (+ 2)
|-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-|-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}--|-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-{}-| \newline % Row Count 11 (+ 2)
| {\bf{Output Dependency}} | Current inputs only            | Current inputs + past states  | \newline % Row Count 13 (+ 2)
| {\bf{Memory}}           | No memory                     | Has memory (e.g., flip-flops) | \newline % Row Count 15 (+ 2)
| {\bf{Feedback}}         | No feedback loop              | Includes feedback loop        | \newline % Row Count 17 (+ 2)
| {\bf{Clock Signal}}     | Not required                  | Requires a clock signal       | \newline % Row Count 19 (+ 2)
| {\bf{Time Dependency}}  | Outputs appear immediately    | Outputs depend on clock cycles | \newline % Row Count 21 (+ 2)
 {\bf{Examples}} \newline % Row Count 22 (+ 1)
- {\bf{Combinational Circuit}}: \newline % Row Count 23 (+ 1)
  - Half Adder: Adds two inputs, outputs Sum = \textbackslash{}( A XOR B ), Carry = \textbackslash{}( A AND B ). \newline % Row Count 25 (+ 2)
- {\bf{Sequential Circuit}}: \newline % Row Count 26 (+ 1)
  - D Flip-Flop: Stores 1 bit of data; updates on clock edge. \newline % Row Count 28 (+ 2)
 {\bf{Applications}} \newline % Row Count 29 (+ 1)
- {\bf{Combinational Circuits}}: \newline % Row Count 30 (+ 1)
} \tn 
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\mymulticolumn{1}{x{3.833cm}}{\bf\textcolor{white}{Combinational Logic (cont)}}  \tn
\SetRowColor{white}
\mymulticolumn{1}{x{3.833cm}}{  - Adders, multiplexers, encoders, decoders. \newline % Row Count 1 (+ 1)
- {\bf{Sequential Circuits}}: \newline % Row Count 2 (+ 1)
  - Counters, shift registers, memory units. \newline % Row Count 3 (+ 1)
{\bf{Summary}} \newline % Row Count 4 (+ 1)
- {\bf{Combinational Circuits}}: \newline % Row Count 5 (+ 1)
  - Simple, stateless, used for logical operations. \newline % Row Count 7 (+ 2)
- {\bf{Sequential Circuits}}: \newline % Row Count 8 (+ 1)
  - Complex, state-based, used for time-sensitive or memory-based tasks. \newline % Row Count 10 (+ 2)
{\bf{For AND(also minterm) gates}} \newline % Row Count 11 (+ 1)
- {\bf{Identity}}: AND-ing anything with `1` keeps it the same. \newline % Row Count 13 (+ 2)
- {\bf{Null}}: AND-ing anything with `0` makes it `0`. \newline % Row Count 15 (+ 2)
- {\bf{Commutative}}: Changing the order of inputs doesn't matter. \newline % Row Count 17 (+ 2)
- {\bf{Associative}}: Grouping inputs in any way doesn't matter. \newline % Row Count 19 (+ 2)
-{\bf{Minterm}} = A⋅B‾⋅C⋅D‾ \newline % Row Count 20 (+ 1)
	- {\bf{sum of products}}: \seqsplit{Y=(A⋅B‾⋅C⋅D)+(A‾⋅B⋅C⋅D‾)+(A⋅B⋅C‾⋅D‾)} \newline % Row Count 22 (+ 2)
{\bf{For OR(maxterm) gate}} \newline % Row Count 23 (+ 1)
- {\bf{Identity}}: \textbackslash{}( A + 0 = A \textbackslash{})  \newline % Row Count 24 (+ 1)
- {\bf{Null}}: \textbackslash{}( A + 1 = 1 \textbackslash{})  \newline % Row Count 25 (+ 1)
- {\bf{Commutative}}: \textbackslash{}( A + B = B + A \textbackslash{})  \newline % Row Count 26 (+ 1)
- {\bf{Associative}}: \textbackslash{}( A + (B + C) = (A + B) + C \textbackslash{}) \newline % Row Count 28 (+ 2)
- {\bf{Idempotent}}: \textbackslash{}( A + A = A \textbackslash{})  \newline % Row Count 29 (+ 1)
- {\bf{Distributive}}:  \newline % Row Count 30 (+ 1)
} \tn 
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\SetRowColor{white}
\mymulticolumn{1}{x{3.833cm}}{	- Over AND: \textbackslash{}( A + (B AND C) = (A + B) AND (A + C) \textbackslash{})  \newline % Row Count 2 (+ 2)
	- Over OR: ( A + (B + C) = (A + B) + C ) \newline % Row Count 3 (+ 1)
-{}- {\bf{Maxterm}} = (A‾+B+C‾+D) \newline % Row Count 4 (+ 1)
- {\bf{Product of sums}}: \seqsplit{Y=(A‾+B+C‾+D)⋅(A+B‾+C+D‾)⋅(A‾+B‾+C‾+D)} \newline % Row Count 6 (+ 2)
Prority Encoder \newline % Row Count 7 (+ 1)
{\bf{Definition}}:   \newline % Row Count 8 (+ 1)
A Priority Encoder is a combinational circuit that encodes the position of the highest-priority active input into a binary output. \newline % Row Count 11 (+ 3)
{\bf{Key Features}}: \newline % Row Count 12 (+ 1)
- {\bf{Inputs}}: \textbackslash{}( 2\textasciicircum{}n \textbackslash{}) input lines; only one active at a time is expected. \newline % Row Count 14 (+ 2)
- {\bf{Outputs}}: \textbackslash{}( n \textbackslash{}) output lines representing the binary code of the highest-priority input. \newline % Row Count 16 (+ 2)
- {\bf{Priority}}: Higher-order inputs have precedence over lower-order inputs. \newline % Row Count 18 (+ 2)
- {\bf{Enable Output}}: Indicates if any input is active (optional). \newline % Row Count 20 (+ 2)
{\bf{Logic Expressions (4-to-2 Priority Encoder)}}: \newline % Row Count 21 (+ 1)
- Y\_1 = D\_3 + D\_2  \newline % Row Count 22 (+ 1)
- Y\_0 = D\_3 +\{D\_2\}‾ * D\_1 \newline % Row Count 23 (+ 1)
- Enable Output (E  =  D\_3 + D\_2 + D\_1 + D\_0  \newline % Row Count 24 (+ 1)
{\bf{Applications}}: \newline % Row Count 25 (+ 1)
1. {\bf{Interrupt Handling}}: Assigns priority to multiple interrupt signals in processors. \newline % Row Count 27 (+ 2)
2. {\bf{Data Compression}}: Encodes multiple inputs into fewer bits. \newline % Row Count 29 (+ 2)
3. {\bf{Memory Decoding}}: Selects the highest-priority address or resource. \newline % Row Count 31 (+ 2)
} \tn 
\end{tabularx}
\par\addvspace{1.3em}

\vfill
\columnbreak
\begin{tabularx}{3.833cm}{X}
\SetRowColor{DarkBackground}
\mymulticolumn{1}{x{3.833cm}}{\bf\textcolor{white}{Combinational Logic (cont)}}  \tn
\SetRowColor{white}
\mymulticolumn{1}{x{3.833cm}}{{\bf{Advantages}}: \newline % Row Count 1 (+ 1)
- Handles multiple inputs with priority logic. \newline % Row Count 2 (+ 1)
- Compresses input size efficiently. \newline % Row Count 3 (+ 1)
{\bf{Limitations}}: \newline % Row Count 4 (+ 1)
- Requires additional handling if multiple inputs have the same priority. \newline % Row Count 6 (+ 2)
- Extra circuitry needed for "no active input" conditions. \newline % Row Count 8 (+ 2)
Causes of Delay in Circuit State Change (Low to High) \newline % Row Count 10 (+ 2)
{\bf{Definition}}:   \newline % Row Count 11 (+ 1)
Delays occur when a circuit element transitions from `0` (low) to `1` (high) due to physical and electrical factors. \newline % Row Count 14 (+ 3)
{\bf{Key Causes of Delay}} \newline % Row Count 15 (+ 1)
1. {\bf{Propagation Delay}}: \newline % Row Count 16 (+ 1)
   - Time taken for a signal to propagate through a circuit element. \newline % Row Count 18 (+ 2)
   - Affects overall circuit speed. \newline % Row Count 19 (+ 1)
2. {\bf{Gate Capacitance}}: \newline % Row Count 20 (+ 1)
   - Time required to charge or discharge the transistor's gate capacitance. \newline % Row Count 22 (+ 2)
3. {\bf{Load Capacitance}}: \newline % Row Count 23 (+ 1)
   - Higher load capacitance slows the charging/discharging process. \newline % Row Count 25 (+ 2)
4. {\bf{Resistance of Interconnects}}: \newline % Row Count 26 (+ 1)
   - Higher resistance in wires increases \textbackslash{}( RC \textbackslash{}) delay. \newline % Row Count 28 (+ 2)
5. {\bf{Signal Rise Time}}: \newline % Row Count 29 (+ 1)
   - Time taken for the signal to rise from 10\% to 90\% of its final value. \newline % Row Count 31 (+ 2)
} \tn 
\end{tabularx}
\par\addvspace{1.3em}

\vfill
\columnbreak
\begin{tabularx}{3.833cm}{X}
\SetRowColor{DarkBackground}
\mymulticolumn{1}{x{3.833cm}}{\bf\textcolor{white}{Combinational Logic (cont)}}  \tn
\SetRowColor{white}
\mymulticolumn{1}{x{3.833cm}}{6. {\bf{Threshold Voltage}}: \newline % Row Count 1 (+ 1)
   - Higher voltage thresholds cause slower transitions. \newline % Row Count 3 (+ 2)
7. {\bf{Noise and Signal Integrity}}: \newline % Row Count 4 (+ 1)
   - Crosstalk, interference, or power fluctuations can distort signals. \newline % Row Count 6 (+ 2)
8. {\bf{Power Supply Voltage}}: \newline % Row Count 7 (+ 1)
   - Lower voltages reduce drive strength, increasing delay. \newline % Row Count 9 (+ 2)
9. {\bf{Temperature Effects}}: \newline % Row Count 10 (+ 1)
   - High temperatures slow down transistor switching. \newline % Row Count 12 (+ 2)
10. {\bf{Manufacturing Variations}}: \newline % Row Count 13 (+ 1)
    - Fabrication inconsistencies can result in slower components. \newline % Row Count 15 (+ 2)
11. {\bf{Clock Synchronization}}: \newline % Row Count 16 (+ 1)
    - Skew or jitter in clock signals causes timing delays in sequential circuits. \newline % Row Count 18 (+ 2)
12. {\bf{Parasitic Elements}}: \newline % Row Count 19 (+ 1)
    - Unintended resistance, capacitance, or inductance contributes to delay. \newline % Row Count 21 (+ 2)
{\bf{Summary}}:   \newline % Row Count 22 (+ 1)
Delays result from intrinsic (e.g., propagation, capacitance) and external factors (e.g., noise, temperature). Optimizing design and materials can mitigate these delays.% Row Count 26 (+ 4)
} \tn 
\hhline{>{\arrayrulecolor{DarkBackground}}-}
\end{tabularx}
\par\addvspace{1.3em}

\begin{tabularx}{3.833cm}{X}
\SetRowColor{DarkBackground}
\mymulticolumn{1}{x{3.833cm}}{\bf\textcolor{white}{Sequential Logic}}  \tn
\SetRowColor{white}
\mymulticolumn{1}{x{3.833cm}}{{\bf{State Table for A, B, Clock and XOR gate what is Q?}} \newline % Row Count 2 (+ 2)
To determine the contents of the output register Q, we'll use a {\bf{state table}} that describes the relationship between the inputs A, B, the clock, and the XNOR gate, along with the resulting Q. \newline % Row Count 6 (+ 4)
 {\bf{XNOR Gate Logic}} \newline % Row Count 7 (+ 1)
- The output of an XNOR gate is A↔B (logical equivalence): \newline % Row Count 9 (+ 2)
    - A ⊕ B = 0: ( A ⊕ B )‾= 1(when A = B) \newline % Row Count 10 (+ 1)
    - A⊕B=1 ( A ⊕ B )‾ = 0:  (when A≠B) \newline % Row Count 11 (+ 1)
The output Q of the register will update on every clock edge based on the XNOR output. \newline % Row Count 13 (+ 2)
 {\bf{State Table}} \newline % Row Count 14 (+ 1)
Assume: \newline % Row Count 15 (+ 1)
- Inputs A and B are parallel inputs (change at each clock cycle). \newline % Row Count 17 (+ 2)
- Register Q is updated at every {\bf{positive clock edge}} with the XNOR output.% Row Count 19 (+ 2)
} \tn 
\hhline{>{\arrayrulecolor{DarkBackground}}-}
\end{tabularx}
\par\addvspace{1.3em}


% That's all folks
\end{multicols*}

\end{document}